1. Field of Use
The present invention relates to data processing systems and, more particularly, to fault tolerant processors.
2. Prior Art
As data processors become entrusted with performing increasingly more critical tasks requiring high dependability, this increases the need for such processors to be fault tolerant. The goal of a fault tolerant design has been stated as one to improve dependability by enabling a system to perform its intended function in the presence of a given number of faults.
Fault tolerance in data processing systems has been achieved through redundancies in hardware, software, information and/or computations. A fault tolerance strategy is considered to include one or more of the following elements. It includes masking (dynamic correction of generated errors); containment (prevention of error propagation across defined boundaries); detection of errors (symptoms of faults); diagnosis (identification of the faulty module responsible for a detected error); repair/reconfiguration (elimination or replacement of a faulty component or a mechanism for bypassing it); and system recovery (correction of the system to a state acceptable for continued operation.
One prior art pipelined central processing system includes in each circuit board of the system, one or more unusual event (UEV) detector circuits designed to detect when the pipeline stage associated therewith is exhibiting abnormal behavior. The phrase "abnormal behavior" refers to the performance of operations by a stage which do not make sense in terms of the functions normally performed by such stage. Such detector circuits are capable of detecting abnormal behavior conditions such as an assumption of an unusual machine state which does not make sense in terms of the input signals being applied, the sending or receiving of an improper sequence of commands in which there is an attempt to perform an operation which is inconsistent with a previously performed operation or an attempt to access a firmware control store location which is inconsistent with normal operation.
The interface board of the processor includes special register circuits for storing the system bus address information pertaining to the last physical address presented to the system bus as well as the address pertaining to a last lock memory operation. If a failure occurs in the pipeline stages for any reason, the address contents of the physical address register indicate to the software, the last physical address or I/O channel number that was being used by the processor in connection with accessing the system bus. For further information regarding the above, reference may be made to the copending patent application of George A. Barlow, et al. entitled, "Recovery Method and Apparatus for a Pipelined Processing Unit of a Multiprocessor System" issued as U.S. Pat. No. 5,193,181, on Mar. 9, 1993.
While the above processor provided for the detection of such unusual events, it provided it at the system bus interface level and as such did not permit immediate processor action. That is, normally, the UEV indications were stored in an area of memory for carrying out later diagnostic analysis to determine the faulty element. Also, at the system level, the detection apparatus was not required at high speed. More importantly, the apparatus only had the capability to detect incorrect sequences of commands being issued by the processor to the system bus.
Accordingly, it is a primary object of the present invention to provide apparatus for monitoring the protocol of a high performance microprocessor.